Features

• Generate timing diagrams directly from VHDL or Verilog simulations.
• Generate timing diagrams directly from VCD files.
• Easily draw and edit timing diagrams.
• Easily add pulses with one mouse click.
• Easily add clock synchronous pulses in any signal or bus
• Easily add automatically incrementing and decrementing pulses.
• Undo / Redo
• Timing analysis with min-max delay margins.
• User defined delays and constraints.
• Select transactions and move complete cycles synchronously
• Mouse moves edges and text.
• StateBars to view clock cycles in diagram.
• Text labels to make notes in diagram.
• Period labels to show clock periods and pulse widths.
• TimeWarps compress timing diagram in time.
• Logic simulations. DFF, Binary Counters, Inverter, Buffer, Differential Driver (More functions coming)
• Timing diagrams files are text formatted files for easy user control.
• Image preview showing diagram within common page sizes.
• Cross platform. Will run on any system with Java Virtual Machine JRE1.6.0 or newer.
• Recent file history to quickly load any of last 20 files
• Automatically loads timing diagrams left open from last session
• Save diagrams as JPG, GIF, PNG image files, and PS, PDF, and SVG formats.
• User control of color settings, fonts, font sizes, and more
• User scripts in Python.
• User scripts create custom features.
• User scripts generate test vectors and testbench files.
• User scripts quickly draw complex timing diagrams.