Step by Step Example

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_images/mem_read_cycle.png

The Timing Diagram Specifications

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Signal Name Freq Duty Cycle Edge Times Start State Format
CLOCK 50MHz 50% 2nS H  
ADD[15:0]     2nS Z Hex
CS*     2nS H  
DATA[7:0]     2nS Z Hex
RD_STROBE*     2nS H  
WR_STROBE*     2nS H  

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Delays Min Typ Max
tclkadd 7nS 10nS 12nS
tpd 7nS 10nS 12nS
tacc 15nS 20nS 25nS
tclk2q 2nS 3nS 4nS

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Constraints Min Typ Max
tsetup 12nS 12nS 12nS
thold 1nS 1nS 1nS

Start a New Timing Diagram

  • To start a diagram, File Menu -> New or Ctrl-n

    1. Start a new timing diagram.

Add the User Defined Constraints and Delays.

  • To add a User Delay, Add Menu -> Delay or Ctrl-7, select User Delay tab in panel.

  • To add a User Constraint, Add Menu -> Constraint or Ctrl-8, select User Constraint tab in panel.

    1. Add the Delays shown above.
    2. Add the Constraints shown above.

Adding the Signals

  • To add a Clock, Add Menu -> Clock or Ctrl-1

  • To add a Signal, Add Menu -> Signal or Ctrl-2

  • To add a Bus, Add Menu -> Bus or Ctrl-3

    1. Add Clock CLOCK.
    2. Add Bus ADD.
    3. Add Signal CS*.
    4. Add Bus DATA.
    5. Add Signal RD_STROBE*.
    6. Add Signal WR_STROBE*.

Adding the Pulses to the Signals

  • To enable “Add Pulse” mode, click on AP button. Button background color turns dark.

  • To disable “Add Pulse” mode, click on AP button. Button background color turns light.

    1. Enable “Add Pulse” mode.
    2. Set “Auto Increment” in toolbar to 0.
    3. Set signal value in toolbar to FFC0.
    4. Click in ADD bus at 30ns,50ns, and 70nS. This will make a FFC0 pulse for 3 clock cycles.
    5. Select “L”. Click in CS* at 50nS and 70nS. This will make a low pulse for 2 clock cycles.
    6. Change signal value to 55. Click in DATA bus at 70nS. This will make a 55 pulse for 1 clock cycle.
    7. Select “L”. Click in RD_STROBE* at 70nS. This will make a low pulse for 1 clock cycle.
    8. Disable “Add Pulse” mode.

Adding the Delays and Constraints

  • To add a Delay, Add Menu -> Delay or Ctrl-7 or right button click for pop-up menu

  • To add a Constraint, Add Menu -> Constraint or Ctrl-8 or right button click for pop-up menu

  • To add a previously used Delay, right button click for pop-up menu and select “Add Used Delay”

  • To add a previously used Constraint, right button click for pop-up menu and select “Add Used Constraint”

    1. Select 1st rising edge of CLOCK and 1st edge of ADD. Add delay tclk2add.
    2. Select 1st edge of ADD and 1st edge of CS*. Add delay tpd.
    3. Select 1st edge of CS* and 1st edge of DATA. Add delay tacc.
    4. Select 1st edge of DATA and 4th rising edge of CLOCK.
    5. Add Constraint. Select Max-Min Type. Add constraint tsetup.
    6. Select 4th rising edge of CLOCK and 2nd edge of ADD. Add delay tclk2q.
    7. Select 4th rising edge of CLOCK and 2nd edge of CS*. Add previously used delay tclk2q
    8. Select 4th rising edge of CLOCK and 2nd edge of DATA. Add previoulsy used delay tclk2q
    9. Select 4th rising edge of CLOCK and 2nd edge of DATA. Select Max-Min. Add constraint thold.
    10. Select 4th rising edge of CLOCK and 2nd edge of RD_STROBE*. Add delay tclk2q
    11. Click in delay and contraint labels in diagram and then use the arrow key combinations to position the labels.

Adding the StateBars

  • To add a StateBar, Add Menu -> StateBar or Ctrl-4

    1. Select 1st rising edge of CLOCK. Add StateBar S1 using dialog.
    2. Select 2nd rising edge of CLOCK. Add StateBar S2 using dialog already open.
    3. Select 3nd rising edge of CLOCK. Add StateBar S3 using dialog already open.
    4. Select 4nd rising edge of CLOCK. Add StateBar S1 using dialog already open.

Timing Analysis

You could increase the CLOCK frequency or change any of the delays to quickly check for constraint violations. This will indicate problems with fast clock rates or slower parts. Drag a Delay or Constraint edge to see the results immediately.